HDB3编译码电路的FPGA设计  

Design of HDB3 Codec Based on FPGA

作　　者：卢晶琦[1] 

机构地区：[1]电子科技大学中山学院,广东中山528402

出　　处：《现代电子技术》2008年第16期1-2,共2页Modern Electronics Technique

基　　金：电子科技大学中山学院青年科技基金资助项目(2006Y05)

摘　　要：HDB3码(3阶高密度双极性码)保持AMI码极性反转的特点,减少连0串的长度,有利于提取定时信息,广泛用于数字通信系统中。针对现有HDB3编码器中存在编码复杂、输出延时长等缺点,设计一种统一位置判断和极性判断的HDB3编码器,并从实际应用出发,将误码检测和位同步提取融入译码器芯片中。仿真和实测表明,编译码功能正确,且相对延时较小、灵活性高,具有实用价值。The HDB3 code（high density bipolar order3 encoding） keeps the feature of polarity inversion of AMI code, which reduces the length of zeros, therefore beneficial for extraction of timing message. To solve the drawbacks of the existing HDB3 encoders,a HDB3 encoder based on block encoding unified polarity judgement and position polarity judgment is proposed. Besides,a HDB3 decoder which contains error detection and timing message distiller is also discussed from the practical view. Simulation and practice results show the new HDB3 Codec have a right function and can be applied to actual circuits.

关 键 词：HDB3码 编译码器 FPGA VHDL 

分 类 号：TN79[电子电信—电路与系统]