二进制数开任意正整数次方运算的硬件方法  

Novel method of extraction for binary based on hardware

作　　者：赖大彧[1] 刘荣科[1] 

机构地区：[1]北京航空航天大学电子信息工程学院,北京100191

出　　处：《北京航空航天大学学报》2008年第8期940-943,共4页Journal of Beijing University of Aeronautics and Astronautics

摘　　要：一种适合于硬件的、普适的、开任意次方的方法,从左至右进行计算,首先得到开方结果的高位,最后得到低位.应用到FPGA(Field Programmable Gate Array)中,与查表结合,对不同的开方次数,模块修改非常方便,普适性较高.该方法消耗的时间与开方的次数呈线性关系.在对一个12 bit数开三次方时,消耗的时间不足传统循环搜索法的50%,所消耗的存储空间不足传统的查表法的2%,并且存储空间上的优势在被开方位数越大的时候越明显.更重要的是,该方法所用的模块只需修改数据位宽和循环次数两处地方就可以提高到任意的精度.A method of any order extraction, works from left to right, which is based on hardware and calculates out the most significant bit（MSB） of the result first and the least significant bit（LSB） last. While applied in field programmable gate array（FPGA） , the method can combine with looking up table（LUT）. Using this method, the occupying time is linear to the extraction order. While doing a 3 order extraction for a 12 bit data, the occupying time of this method is 50% less than the traditional searching method, and the occup- ying memory is only 2% that of traditional method of LUT. As the order of extraction grows, the superiority will be more obvious. More important, the module only need to be modified in 2 point, the precision can be improved as wanted.

关 键 词：开方 硬件 VERILOG HDL 

分 类 号：TP312[自动化与计算机技术—计算机软件与理论]