并行CORDIC算法的研究及FPGA实现  

Research of the Parallel CORDIC Algorithm and Its Implementation in FPGA

作　　者：雷元武[1] 周杰[1] 葛颖增[2] 窦勇[1] 

机构地区：[1]国防科技大学计算机学院,湖南长沙410073 [2]河南公安高等专科学校信息安全系,河南郑州450002

出　　处：《计算机工程与科学》2008年第8期75-78,共4页Computer Engineering & Science

基　　金：国家自然科学基金资助项目(60633050)

摘　　要：本文讨论旋转模式下CORDIC算法的符号预测和迭代计算问题,采用并行计算方法来加速CORDIC算法。文中提出分段符号预测和增加校正迭代的符号预测机制,使用分段迭代展开和三输入加法树来完成CORDIC算法的迭代计算,有效地减少了计算的级数和硬件开销,提高了计算性能。最后,在Altera的StratixII芯片上实现了并行CORDIC结构。This paper discusses the sign prediction and iterative calculation of the CORDIC algorithm in the rotation mode, and uses a parallel computation technique to accelerate it. We propose the sign prediction mechanism of subsection sign prediction and adding the correcting rotation, and use a method of unfolded subsection iteration and a three-in adder tree to perform the iterative calculation of the CORDIC algorithm. These techniques effectively reduce the correcting rotations and the cost of hardware, and enhance the computing performance. Finally the parallel CORDIC architecture is implemented on the FPGA chip of StratixlI from Altera.

关 键 词：CORDIC 符号预测 FPGA 

分 类 号：TP302[自动化与计算机技术—计算机系统结构]