高速SERDES的多板传输技术与SI仿真  

The Multi-Board Transmission Technology and the SI Simulation for High-Speed SERDES Design

作　　者：曹跃胜[1] 胡军[1] 刘烨铭[1] 

机构地区：[1]国防科技大学计算机学院,湖南长沙410073

出　　处：《计算机工程与科学》2008年第8期139-143,共5页Computer Engineering & Science

基　　金：国家自然科学基金资助项目(60676016)

摘　　要：随着SERDES传输速率达到10Gbps,高速PCB上的信号传输尤其是多板间传输,已经成为高速设计的实现难点。高速PCB及其要素的设计、分析、仿真,以及高速传输链路的设计优化,是多板SERDES传输实现更高速率的关键。本文对高速串行SERDES的原理和架构进行了深入分析,研究了多板传输中影响信号完整性(SI)的关键因素和建模优化方法;最后,针对实验电路板建立了多板仿真模型,对实际的SERDES差分网络进行了仿真分析。With the SERDES data rate approaching 10 Gbps, the transmission technology of PCB, especially the multiboard transmission, has become more and more difficult. Understanding, designing and simulating the PCB and its features as precisely as possible is essential for optimizing the complete signal path, and the very high-speed serial links can be achieved. This paper firstly analyzes the framework of SERDES, and then studies and models the key features of the high- speed PCB design. As a result , the multi-board transmission model is built by using the experimental PCBs, and the key SERDES network transmission on multi-PCBs are simulated and analyzed.

关 键 词：传输线 特性阻抗 信号完整性 连接器 过孔 高速串行传输 IBIS SPICE 多板分析 电路仿真 

分 类 号：TP336[自动化与计算机技术—计算机系统结构] TP303[自动化与计算机技术—计算机科学与技术]