1.6Kb/s类MELP语音压缩编码器的FPGA实现  

FPGA Implementation of a 1.6Kb/s Speech Coding Algorithm

作　　者：郭立[1] 王妙锋[1] 刘璐[1] 郁理[1] 李琳[1] 

机构地区：[1]中国科技大学电子科学与技术系,安徽合肥230027

出　　处：《小型微型计算机系统》2008年第8期1553-1556,共4页Journal of Chinese Computer Systems

摘　　要：基于"CPU软核+模块算法IP"的方法对一个1.6Kb/s类MELP语音压缩编码算法进行了实现,并将整个语音压缩编码器在FPGA上进行了整体验证,实验结果说明本文给出的语音压缩编码器的实现结构是可行的,能够满足语音压缩编码算法对实时性的要求,从而为下一阶段语音压缩编码器的芯片设计提供有力的可行性论据.同时,由于本文给出的语音压缩编码器的实现结构中的各模块算法IP对于许多语音压缩编码算法中都适用,因此该语音压缩编码器的实现结构对不同的语音压缩编码算法具有一定的通用性.Presented a structure of a 1.6 Kb/s speech coding algorithm based on the method of ＂CPU soft core ＋ algorithm IP＂. This structure was implemented on FPGA device, and the experimental results indicate that the structure is feasible, and it can satisfy the real-time requirements that speech coding algorithm needs, it also provide a proof that the structure is feasible for the next stage of the speech chip design. Meanwhile, as the module algorithms IP in this structure can also be applied in many other speech coding algorithms, this structure is universal for the implementation of different speech coding algorithms.

关 键 词：语音压缩编码 MELP FPGA实现 SOC 

分 类 号：TP391[自动化与计算机技术—计算机应用技术]