基于IP核的FPGA FFT算法模块的设计与实现  

Design and Implementation of FPGA FFT Algorithm Module Based on IP Core

作　　者：窦秀梅[1] 赵振纲[1] 

机构地区：[1]北京邮电大学信息工程学院,北京100876

出　　处：《无线电工程》2008年第8期29-31,共3页Radio Engineering

摘　　要：介绍了一种基于IP核的FFT算法的设计与实现方法。FFT IP核允许设置不同的计算参数与结构,可以方便灵活地实现FFT算法。详细分析了FFT IP核的各个参数的意义。研究结果表明,应用FFT IP核能够设计出符合不同性能要求的高性能的傅里叶变换处理模块,缩短开发周期,节约成本。Design and implementation of FFT algorithm based on Ahera IP core is presented. Various parameters and architectures can be set for FFT IP core, FFT algorithm can be realized conveniently and flexibly. Various parameters of the FFT IP core are analyzed in detail and the simulation result is given. The results show that the FFT IP applications can be designed to meet the requirements of various high- performance FFT processing modules and to shorten the development cycle, save the cost.

关 键 词：IP核 FFT CYCLONE Ⅲ FPGA 短时傅里叶变换 

分 类 号：TP332.3[自动化与计算机技术—计算机系统结构]