低功耗全加器的电路设计  

Low-power design for full adder circuits

作　　者：张爱华[1] 夏银水[1] 

机构地区：[1]宁波大学电路与系统研究所,浙江宁波315211

出　　处：《浙江大学学报（理学版）》2008年第5期534-537,共4页Journal of Zhejiang University（Science Edition）

基　　金：国家自然科学基金资助项目(60676017);浙江省自然科学基金人才培养专项资助项目(R105614);宁波市自然科学基金资助项目(2006A610091)

摘　　要：在对现有全加器电路研究分析的基础上,提出了基于传输管逻辑的低功耗全加器.所建议的电路采用对称结构平衡电路延迟,削减了毛刺,降低了功耗.采用TSMC0.24μmCMOS工艺器件参数情况下,对所设计的低功耗全加器进行PSPICE模拟.模拟结果表明,在3.3V和1.8V电源电压下,与已发表的全加器相比,所建议的全加器电路功耗改进可分别高达58.3%和60.8%.Based on studying and analyzing published full adders, a pass transistor based low-power full adder was proposed. The circuit structure of the proposed full adder is symmetrical and the circuit delay is balanced, so glitches are cut down, which leads to power consumption reduction. Using the parameters of TSMC 0.24 μm CMOS device, the low power full adder designed was simulated by PSPICE. The simulation results showed that the power savings of the proposed adder was improved up to 58.3% and 60.8% at 3.3 V supply voltages and 1.8 V supply voltages, respectively, as compared with the published adders.

关 键 词：低功耗 全加器 传输晶体管 

分 类 号：TN432[电子电信—微电子学与固体电子学]