一种H.264/AVC解码器关键技术的设计  

Design of the key Technology in H.264/AVC Decoder

作　　者：谭立地[1] 林浩[1] 徐昕[1] 周娅[2] 

机构地区：[1]江西省科学院,江西南昌330029 [2]华中科技大学,湖北武汉430074

出　　处：《江西科学》2008年第4期608-610,661,共4页Jiangxi Science

摘　　要：本文提出了H.264/AVC解码器的系统结构及其核心单元总体结构的设计研究方案。重点包括系统的流水线设计、双总线设计以及IDCT变换、帧内预测、帧间运动补偿等关键模块的设计与大规模逻辑实现。硬件解码部分在200 MHz系统时钟时可以实时解码H.264 High 4:4:4 profile 4.0 level码流。This paper proposed the architecture of the H.264/AVC decoding system and shared the design research plan of its core unit. The research covered the design of some key modules and its large-scale logical implementation. The covered topics are ： the overall system pipeline design, the dual-bus design, the IDCT transformation, the inter prediction, and the frame motion compensation. The hardware decoder can decode one bit stream, complied with H. 264 specification High 4：4：4 profile 4.0 level bit stream,in real time running a svstem clock at 200 MHz.

关 键 词：H.264/AVC 解码器 关键技术 VLSI/ASIC/SoC 

分 类 号：TN919.81[电子电信—通信与信息系统] TP751.1[电子电信—信息与通信工程]