卷积码编码器和Viterbi译码器的FPGA实现  

Implementation of Convolution Code Encoder and Viterbi Decoder Based on FPGA

作　　者：牟崧友[1] 

机构地区：[1]南京邮电大学,江苏省南京市210003

出　　处：《电子工程师》2008年第8期21-24,共4页Electronic Engineer

摘　　要：Viterbi译码是对卷积码的一种最大似然译码算法。主要介绍卷积码的Viterbi译码器的FPGA(现场可编程门阵列)实现方案。根据卷积码的特点,设计了用寄存器交换法存储幸存路径的模块,充分利用FPGA触发器资源丰富的优点。同时,为使系统在保持同等性能条件下可以高效率实现,对Viterbi译码实现中的数据溢出和输出判决部分进行了优化,处理的结果使得系统的性能和效率都有提高。本设计已基于FPGA实现,译码速度快、延时小。Viterbi decoding algorithm based design and implementation of RSC is a maximum likelihood algorithm for the convolutional code. FPGA Viterbi decoder is presented in this paper. Abundant flip flop re- source of FPGA made it possible to design a survival path exchange register module according to the trait of RSC. At the same time, for the sake of realizing data overflowing and decision parts are optimized the system of higher efficiency with the same performance, in the system implementation. The results of optimization show that both the system performance and efficiency are improved. A FPGA-based Viterbi decoder was obtained. On the basis of the results, its advantages in decoding speed and time delay was demonstrated as well.

关 键 词：卷积编码 VITERBI算法 FPGA 寄存器交换法 

分 类 号：TN911.22[电子电信—通信与信息系统]