H.264 ABT与量化器的硬件设计与实现  

Hardware design and implementation of H.264 ABT and quantizator

作　　者：胡琛[1] 张宇弘[1] 

机构地区：[1]浙江大学超大规模集成电路研究所,浙江杭州310027

出　　处：《机电工程》2008年第9期14-17,共4页Journal of Mechanical & Electrical Engineering

摘　　要：基于自适应块划分尺寸变换(ABT)和8×8整数DCT(IDCT)与量化的实现算法,改进了现有的4×4整数DCT与量化算法。利用两种变换算法可合并性和量化的相似性,设计了可复用ABT和量化器的硬件电路,并使用Verilog语言对该设计进行了超大规模集成电路(VLSI)实现,采用SMIC 0.18μm工艺,综合后的电路关键路径最大延时为11.94 ns,电路面积为1.20 mm2。实验对比结果表明,本设计在基本不增加面积的情况下,使得原来只能处理8×8的IDCT和量化器也能处理4×4 IDCT与量化,增强了硬件电路的适应性,同时也提高了系统的灵活性。Based on the concept of adaptive block transforms（ABT） and algorism of 8 × 8 integral DCT and quantization implementation, the algorism of 4 × 4 integral DCT and quantization implementation were improved, and the multiplex ABT and quantizator were designed because of the similarity of two algorisms. It was prototyped using Verilog HDL language and implemented using SMIC 0.18 μm technology. The length of critical path is 11,94 ns after synthesis, and the area of the system is 1.20 mm^2. According to the experimental data, the circuit makes the common IDCT and quantizator for 8 × 8 blocks can also process the 4 × 4 blocks with little increase of area. It improves the suitability of the circuit and the flexibility of the system.

关 键 词：超大规模集成电路 H.264 自适应块划分尺寸变换 整数DCT 量化 

分 类 号：TP331.1[自动化与计算机技术—计算机系统结构]