一种2 Gbps的多数据包透明传输机制  

A 2 Gbps transparent mechanism for multi-packet transmitting

作　　者：宁元辉[1] 朱光喜[1] 苏钢[1] 谭力[1] 

机构地区：[1]华中科技大学电子与信息工程系,武汉430074

出　　处：《高技术通讯》2008年第9期881-887,共7页Chinese High Technology Letters

基　　金：863计划(2003AA12331005)资助项目

摘　　要：基于模块化设计方法对 RocketIO 发送器的吉比特数据发送策略进行了深入研究,提出了一种速率为2Gbps 的多数据包透明传输的机制。根据此机制,仅配置3个包格式寄存器则可实现对 RAM 内数据以任意要求的格式发送,从而解决了利用 RocketIO 发送数据固有的可升级性差的问题。该透明发送机制展示出其运用 Verilog HDL 高级语言的设计思想,以及升级性好、复杂度低、实现简单的优点。该方案已在 Xilinx 公司的现场可编程门阵列(FPGA)器件 XC2VP20上得到了实现,验证了基于这一发送机制的设计方法的有效性和可行性。该研究对其它高速串行数据传输标准具有广泛的应用价值。Based on the module design method, the gigabit data sending strategy of the RocketIO transceiver is deeply investigated in this paper. A 2 Gbps transparent mechanism for multi-packet transmitting is proposed. According to the proposed scheme, the data in RAM can be sent in any required format by configuring three packet format registers, which solves the inherent problem of weak scalability when using RocketIO to transmit data. This transparent transmission mechanism shows the advanced language design method of Verilog HDL and has the advantages of scalability, low complexity, and easy implementation. The scheme has been implemented in XC2VP20, a field-programmable gate array （FPGA） developed by the Xinlinx, which validates the effectiveness and feasibility of the design based on the mechanism. The research has wide usage in other high speed serial data transfer standards.

关 键 词：透明数据发送 ROCKETIO AURORA FPGA实现 

分 类 号：TN919.1[电子电信—通信与信息系统]