用于CDR电路的相位插值选择电路设计  

Design of Phase Interpolation and Selection Circuit for CDR

作　　者：曾泽沧[1] 邓军勇[1] 蒋林[1] 

机构地区：[1]西安邮电学院计算机系,西安710061

出　　处：《半导体技术》2008年第8期721-725,共5页Semiconductor Technology

基　　金：国家"863"计划项目(2003AA1Z1190);陕西省科技攻关项目(2004k05-G4);西安邮电学院中青年科研基金项目(ZL2007-15)

摘　　要：时钟数据恢复电路是高速多通道串行收发系统中接收端的关键电路,其性能的优劣直接影响了整个系统的功能。描述了双环时钟数据恢复电路利用相位正交的参考时钟进行工作的原理,分析了传统的正交时钟产生方案,提出一种新的相位插值-选择方案并给出了CMOS电路实现。在SMIC0.18μm CMOS工艺下采用Cadence公司的仿真工具Spectre进行了晶体管级验证,结果显示,利用该电路恢复出来的时钟对数据进行重定时,能较好地消除传输过程中积累的抖动,有效地提高了输入抖动容限。Clock and data recovery circuit is a critical circuit in the receiver of high-speed multi-channel serial-data transceiver systems, and its performance affects the entire system function directly. The principle with the quadrature reference clocks in dual-loop clock and data recovery circuit was described. The traditional scheme of generating quadrature clock was analyzed, and a new algorithm with phase interpolation and selection was presented, also the CMOS circuit realization of it was given. The design was verified in SMIC 0.18gin CMOS technology with the simulation tool Spectre of Cadence , ＂and the results show that retiming the data with recovered clock can remove the accumulated jitter during transmission. This scheme has improves the jitter tolerance of input datum.

关 键 词：双环时钟数据恢复 正交相位 相位插值 CMOS电路 

分 类 号：TN47[电子电信—微电子学与固体电子学]