CMOS电荷泵锁相环中鉴频鉴相器的研究与设计  

Research and Design of CMOS Charge Pump PLL PFD

作　　者：李颖[1] 岳松洁[1] 

机构地区：[1]中南林业科技大学电子与信息工程学院,长沙410004

出　　处：《微纳电子技术》2008年第9期551-556,共6页Micronanoelectronic Technology

摘　　要：介绍了鉴频鉴相器(PFD)在其发展过程中产生的结构,并对每一种结构的优缺点进行了比较。通过对原有PFD电路结构进行重新设计,在传统D触发器PFD的基础上提出了两种新型PFD:传输门D触发器型PFD和基于锁存器的PFD。电路设计基于TSMC公司的0.18μm CMOS工艺,仿真环境为Candence Spectre,仿真结果显示电路可以工作在2GHz以上频率的应用环境下。相对于传统的PFD,新型PFD工作频率高、几乎无死区,而且具有噪声低、速度快的优点,在高速、低抖动、低噪声PLL中将有广泛的应用前景。The development and the structures of the phase frequency detector （PFD） were introduced. The advantages and disadvantages of these structures were compared. Through redesigning the structure of the original PFD circuit and based on the traditional D trigger PFD, two new PFDs, transmission gate D trigger PFD and flip-latch based PFD were proposed. The circuit design was based on 0. 18 μm CMOS technology which belongs to TSMC company, the simulation environment is Candence Spectre. The simulation result demonstrates that the circuit can performance well in the work environment which the frequency is beyond 2 GHz. Comparing with the traditional PFD, the major advantages of the new PFD are high frequency, nearly no dead zone, low noise and high speed. This kind of PFD will be widely used in the high speed, low jitter, low noise PLL.

关 键 词：鉴频鉴相器 锁相环 死区 D触发器 锁存器 

分 类 号：TN432[电子电信—微电子学与固体电子学] TN402