JTAG标准及其与16位微处理器IP软核的集成  

JTAG standard and its integration with 16-bit microprocessor soft IP

作　　者：张建生[1] 李洋[1] 宋何娟[1] 缪庭[1] 

机构地区：[1]合肥工业大学电气与自动化工程学院,安徽合肥230009

出　　处：《合肥工业大学学报（自然科学版）》2008年第9期1365-1368,1407,共5页Journal of Hefei University of Technology：Natural Science

基　　金：国家自然科学基金资助项目(60576034)

摘　　要：随着集成电路规模的越来越大,可测性设计越来越受到业内的关注,基于JTAG标准的可测性设计是当前的研究热点之一;文章首先介绍了JTAG标准,进而详细讨论了JTAG模块的设计、与16位微处理器IP软核的集成方法与实践;然后介绍了一种模块化设计的方法,具有较强的实用性和可移植性。With the increasing of the scale of integrated circuits （IC）, Design-for-Test （DFT） attracts much more attention in IC design industry, and JTAG research is one of the hot issues in DFT. The JTAG standard is introduced first in this paper. Then the JTAG design and the method for integration of 16-bit microprocessor soft IP and simulation results are discussed in detail. A method of modularization design is introduced and it has better modifiability and transportability.

关 键 词：可测性设计 联合测试行动小组 模块化设计 

分 类 号：TP368.1[自动化与计算机技术—计算机系统结构]