基于线性规划的关键面积最小化方法  

Critical Area Minimization Using the LP Method

作　　者：王强[1] 王俊平[1] 任春丽[1] 

机构地区：[1]西安电子科技大学通信工程学院,陕西西安710071

出　　处：《电子科技》2008年第10期1-4,共4页Electronic Science and Technology

基　　金：西安AM创新基金资助项目(XA-AM-200601);西安市科技计划资助项目(CXY08018)

摘　　要：随着集成电路(IC)技术的不断发展,尤其在90nm和65nm技术节点,集成电路制造业的投资剧增而随机成品率却在下降。为了提升随机成品率,需要在布线或后布线阶段减小关键面积。文中提出一种基于线性规划降低关键面积的方法,使关键面积在一组条件约束下,通过版图中一些特征量的变化,建立起一个线性规划模型,然后求其最优解,进而得出关键面积的最小值。该方法的优点是把一个版图优化问题转化为数学问题,使问题更精确化,从而为成品率的优化提供了一条新途径。For modem IC processes at 90 nm and 65 nm technology nodes, the investment of IC manufacturing is increasing sharply whereas the random yield loss is decreasing. Hence, it is essential to minimize the critical area during routing or post-routing. This paper presents a method using the linear programming method to minimize the critical area which is equivalent to the difference between the original critical areas and uses this model to formulate a set of conditions into linear programming. The main advantages of this method are that it can transform a layout optimization problem into a mathematical problem and make the problem more specific, thus offering a new approach to yield optimization.

关 键 词：关键面积 成品率优化 线性规划 

分 类 号：TN41[电子电信—微电子学与固体电子学]