一种适用于H.264/AVC宏块级反变换编码的IP核设计  

Design of a Macroblock Level Inverse Transform IP Core for H.264/AVC

作　　者：张益林[1] 徐雄[1] 杨宇红[2] 

机构地区：[1]上海交通大学电子工程系,上海200240 [2]上海交通大学电子系图像通信与信息处理研究所,上海200240

出　　处：《中国图象图形学报》2008年第10期2019-2022,共4页Journal of Image and Graphics

摘　　要：本文提出了适用于H.264/AVC宏块级反变换的IP核完整设计方案。首先,使用改进的T型结构同步宏块中的3种不同变换和反Zig-Zag扫描。然后,对Hadamard反变换模块采用了时分复用存储器模块的设计方案,降低了系统时延;再利用IDCT矩阵运算可分离的特点,减少了IDCT模块资源消耗;最后,给出了以Xilinx Viretex2系列XC2V6000为目标器件的综合结果。仿真结果表明,该设计能够正确支持1080i50Hz高清码流的实时解码。A high throughput inverse transform IP core for H. 264/AVC was proposed in this paper. The improved T archlteeture was presented to synchronize three different transforms and inverse Zig-Zag scan module. By applying time multiplexing buffer management to inverse Hadamard transform, we efficiently reduce its latency. Separability property of IDCT is also utilized to minimize its area. At last, the results of synthesis are given with Xilinx Virtex2 while XC2V6000 as the target device. The simulation performance shows that the design can effectively support the real-time decoding of 1080i 50Hz HD stream.

关 键 词：反DCT变换 Hadamard反变换 T型结构 IP核 

分 类 号：TP301.6[自动化与计算机技术—计算机系统结构]