基于RLC模型的互连线时延估算  

Estimation of interconnect delay based on RLC model

作　　者：李朝辉[1] 孙玉楠[2] 

机构地区：[1]燕山大学电子与通信工程系,河北秦皇岛066004 [2]燕山大学教务处,河北秦皇岛066004

出　　处：《计算机工程与设计》2008年第20期5383-5384,5387,共3页Computer Engineering and Design

摘　　要：对VLSI电路中RLC互连线的时延进行了研究,使用改进的一阶模型来近似分布式均匀传输线的传输函数,计算出时域下的阶跃响应并得到简洁的时延计算公式。然后将其应用到具体的RLC互连树中计算源节点到漏节点的时延,其驱动器模型由电阻和电容组成,负载为容性负载。实验结果表明,该模型的计算结果与SPICE仿真结果的误差小于10%,计算量也比基于二阶传输函数的算法大为减少,在计算效率和精度两方面得到较好折衷,可以用于考虑时延效应的优化程序中。By using an improved modified one-pole model, the moment is approximated. Then the step response in time domain system transfer function for distributed uniform lines up to the first and a simple delay formula are both calculated. The formula is also applied in the estimation of source-sink delays in an interconnect tree. The model has a driver, which comprises a resistance and capacitance, and a capacitive load. The results shown that the delay estimates based on the model presented are within 10% of the SPICE computed delay. And the tradeoffbetween accuracy and efficiency is obtained. It can be used in delay-aware layout optimization programs.

关 键 词：集成电路 互连线 时延 RLC互连树 驱动器 

分 类 号：TP39[自动化与计算机技术—计算机应用技术] TN402[自动化与计算机技术—计算机科学与技术]