基于VHDL和FPGA的自适应数字频率计的研究与设计  

Study and design of adaptive digital frequency counter based on VHDL and FPGA

作　　者：孙虹[1] 何宏[1] 张大建[2] 孟晖[2] 张艳[2] 宁书岩 

机构地区：[1]天津理工大学天津市薄膜电子与通信器件实验室,天津300191 [2]天津市计量技术研究所,天津300192

出　　处：《天津理工大学学报》2008年第1期24-27,共4页Journal of Tianjin University of Technology

基　　金：天津市自然科学基金(05YFJMJC13100);天津市社会发展科技重点项目(05YFSYSF033)

摘　　要：基于测频原理及FPGA的设计思想,论述了利用VHDL硬件描述语言设计自适应数字频率计的新方法.此设计自顶而下,采用模块化单元构建系统.通过软件智能设计,突破了以往改变闸门时间的方法,使自动换档的实现更加简单可靠.在具体实现上,使用开发工具ISE6.1进行软件开发,Modelsim进行仿真,并将程序下载到作为自适应数字频率计核心电路的FPGA芯片中.与传统方法比,具有外围电路简单,设计周期短,易于修改等优点.Based on the principle of frequency measurement and the programming thought of FPGA, this paper elaborates on a new method for designing adaptive digital frequency counter by using VHDL. This method is up to bottom and develop the system by using modularization cell. By designing intelligent software, it break though the ol method of changing gate time and make the realization of automatic gear-shifting more easy and reliable. In terms of realization, ISE6.1 developmental tool is adopted to expert software, and Modelsim is used to simulate , and the program is transferred to FPGA which is the core circuit of adaptive digital frequency counter. Comparing with traditional method, this method has the merit of simple peripheral circuit, short design period and easy amendment.

关 键 词：VHDL FPGA 自适应 数字频率计 电路模块 

分 类 号：TU352.110.4[建筑科学—结构工程]