嵌入式处理器动态分支预测机制研究与设计  

Research and Design of Dynamic Branch Prediction Mechanism for Embedded Processor

作　　者：黄伟[1] 王玉艳[1] 章建雄[1] 

机构地区：[1]华东计算技术研究所,上海200233

出　　处：《计算机工程》2008年第21期163-165,共3页Computer Engineering

摘　　要：针对嵌入式处理器的特定应用环境,通过对传统神经网络算法的改进,结合定制的分支目标缓冲,提出一种复合式动态分支预测机制。该机制基于全局索引方式,对BTB结构进行定制设计,实现对循环逻辑中最后一条分支指令的精确预测。实验结果表明,该动态分支预测机制能降低硬件复杂度,提高预测精度。Aiming to the specific application environment of embedded processors, this paper gives a hybrid mechanism which combines custom-designed Branch Target Buffer（BTB） with improved neural network arithmetic for the dynamic branch prediction. In this mechanism, neural network arithmetic implements an approach of global indexing with less resource rather than the normal indexing way based on the instruction address. In use of the unique feature of embedded applications, the BTB structure makes accurate prediction for the final branch instruction in the loop logic. The result indicates that this mechanism achieves high precision with lower complexity.

关 键 词：复合分支预测 神经网络 分支目标缓冲 嵌入式处理器 SimpleScalar模拟 

分 类 号：TP391.4[自动化与计算机技术—计算机应用技术]