基于断言的AHB-Wishbone总线桥的功能验证  

Functional Verification of Assertion Based AHB-Wishbone Bus Bridge in SOC

作　　者：姜伟[1] 王祖强[1] 

机构地区：[1]山东大学信息科学与工程学院,山东济南250100

出　　处：《电气电子教学学报》2008年第5期37-41,共5页Journal of Electrical and Electronic Education

摘　　要：本文比较了AMBA的AHB协议和Wishbone协议,提出使用SystemVerilog语言实现AHB-Wishbone总线桥的方法。文中阐述了如何将SystemVerilog断言嵌入到设计中,监视总线信号的时序关系。结合Mentor公司的高级验证方法学(AVM)搭建验证平台,并对设计进行功能验证,采用了事务级的验证策略以及随机约束和功能覆盖率等验证技术新特性。总线桥验证平台能够极大的提高验证效率,其组件具有可重用性。最后在ModelSim工具下进行了仿真,仿真报告和结果说明了总线桥的设计符合要求。Comparing AHB protocals of AMBA with Wishbone protocols, the paper introduces the method of AHB-Wishbone bus bridge implemented by using hardware description and verification language-SystemVerilog. Assertions are added to the design to monitor timing of bus signals. According to Advanced Verification Methodology, testbench is constructed in order to functionally verify the design, which uses transaction-level strategy, constraint-random and coverage driven methodology. The testbench improves the verification efficiency and reusability. The simulation report and result indicate that the design meets the requirement.

关 键 词：断言 AVM SYSTEMVERILOG 总线桥 

分 类 号：TN402[电子电信—微电子学与固体电子学]