基于SET/MOS混合结构的译码器电路的设计  

Design of a Decoder Circuit with Hybrid Architectures of SET and MOS Transistors

作　　者：李芹[1] 蔡理[1] 王森[1] 吴刚[1] 

机构地区：[1]空军工程大学理学院,陕西西安710051

出　　处：《微电子学与计算机》2008年第11期17-20,共4页Microelectronics & Computer

基　　金：陕西省自然科学基金项目(2005F20);空军工程大学理学院科研项目(2005ZK19)

摘　　要：基于SET的I-V特性以及SET与MOS管互补的特性,以MOS管的逻辑电路为设计思想,首先提出了一个SET/MOS混合结构的反相器,进而推出或非门电路,并最终实现了一个唯一地址译码器.通过SET和MOS管两者的混合构建的电路与纯SET实现的电路相比,电路的带负载能力增强;与纯MOS晶体管实现的电路相比,电路同样仅需要单电源供电,且元器件数目得到了减少,电路的静态功耗大大降低.仿真结果验证了电路设计的正确性.Based on the Ⅰ-Ⅴ characteristics of single- electron transistor and the idea of M（3S digital logic circuits, an inverter using the hybrid SET/MOS transistors was proposed and the NOR gate was expanded. Finally, a novel uniquely address decker was realized using these lcgic circuits, which, compared with the pure SET circuit, is considerably augmented in its drive capabili- W, compared with the IVIGS circuit, it needs likewise one rescxarce support the power, but the number of transistor is decreased and the total static power depletion is reduced. The accuaracy of the circuit is validated by SPICE.

关 键 词：单电子晶体管 MOS管 反相器 或非门 译码器 

分 类 号：TN389[电子电信—物理电子学]