对JFET顶、背栅电位稳定技术分析  

An Analysis of the Potential Stability Technology of JFET Plate Fond and Back Grid

作　　者：李秀芬[1] 李育贤[2] 郝忠民[3] 辛国强[3] 

机构地区：[1]吉林工程技术师范学院教育技术中心,吉林长春130052 [2]西安邮电学院计算机系,陕西西安710121 [3]柳河县职业教育中心,吉林柳河135300

出　　处：《吉林工程技术师范学院学报》2008年第10期70-73,共4页Journal of Jilin Engineering Normal University

摘　　要：在JFET作输入管的低噪声高精度运放中,为了进一步减小输入偏流,增大输入阻抗,可使顶、背栅分离,且仅以顶栅接片内的控制电路。本文主要对JFET背栅电平进行动态稳定控制的电路进行分析。When JFET is used as input tube in the a low- noise and high -operational amplitier, to reduce the input bias and increase input impedance, plate fond and back grid can be separated and the plate fond can receive input Signal alone and back grid connects the control Circuit in the plate. This paper mainly analyzes the control circuit to stabilize dynamically the electrical level in JFET back grid.

关 键 词：JFET 电路 顶、背栅 

分 类 号：TN722[电子电信—电路与系统]