0.5μmCMOS带隙基准电路设计  

Design of bandgap reference circuit with 0.5μm CMOS process

作　　者：张明英[1] 朱刘松[2] 邢立冬[3] 

机构地区：[1]西安外事学院信息工程学院,陕西西安710061 [2]中国人民解放军第323医院信息科,陕西西安710054 [3]西安邮电学院计算机科学与技术系,陕西西安710061

出　　处：《国外电子元器件》2008年第12期79-81,共3页International Electronic Elements

摘　　要：依据带隙基准原理,采用华润上华(CSMC)0.5μm互补金属氧化物半导体(CMOS)工艺,设计了一种用于总线低电压差分信号(Bus Low Voltage Differential Signal,简称BLVDS)的总线收发器带隙基准电路。该电路有较低的温度系数和较高的电源抑制比。Hspice仿真结果表明,在电源电压VDD=3.3 V,温度T=25℃时,输出基准电压Vref=1.25 V。在温度范围为-45℃～+85℃时,输出电压的温度系数为20 pm/℃,电源电压的抑制比δ(PSRR)=-58.3 dB。A bandgap reference circuit which is based on the bandgap voltage theory using for BLVDS transceiver system is designed with CSMC 0.5μm CMOS technology in this paper.This circuit features low temperature coefficient and high power supply rejection ratio.HSPICE simulation results show that the circuit can obtain a stable output voltage Vmf=1.25V when supply voltage is 3.3V and temperature is 25℃.The temperature coefficient of output voltage is 20pm/℃ with a PSRR of -58.3 dB over temperature range from -45℃＋85℃.

关 键 词：模拟电路 电源 温度/带隙基准 抑制比 CMOS工艺 

分 类 号：TN79[电子电信—电路与系统]