35KCMOS器件LDD结构的SPICE宏模型  

SPICE MODEL FOR LDD STRUCTURE CMOS DEVICE AT 35K

作　　者：刘文永[1,2] 丁瑞军[1] 冯琪[1] 

机构地区：[1]中国科学院上海技术物理研究所,上海200083 [2]中国科学院研究生院,北京100039

出　　处：《红外与毫米波学报》2008年第6期465-469,共5页Journal of Infrared and Millimeter Waves

基　　金：预先研究(61501050303)资助项目

摘　　要：针对BSIM3v3模型在35K低温下无法模拟LDD(轻掺杂漏区)所引起的串联电阻异常,提出了可以模拟这一异常的SPICE宏模型.通过修改CMOS器件常温BSIM3v3模型中的一些与温度有关的参数值,得到35K BSIM3v3模型.模拟结果表明,根据此模型进行参数提取后的Ⅰ-Ⅴ特性曲线与实测曲线十分吻合.最后,运用此模型对CMOS传输门和两级运算放大器进行仿真,结果表明LDD串联电阻效应对这些电路产生了重要影响,该模型明显提高了低温BSIM3v3的仿真精度.Since the abnormal series resistance caused by LDD structure for CMOS device at 35K temperature could not be simulated by BSIM3v3 model, new macro models were introduced to represent the change of LDD series resistance. Simulation results exhibit that the I-V characteristics of the macro model match well with the measurement. Finally, the CMOS transmission gate and two-stage amplifier were simulated with new BSIM3v3 model in addition to the macro model. The results reveal that the change of LDD series resistance has obvious effects on low temperature CMOS circuits.

关 键 词：轻掺杂漏区 串联电阻 BSIM3V3 SPICE模型 CMOS 低温 

分 类 号：TN386.1[电子电信—物理电子学]