AVS视频解码器中VLD模块的硬件设计  

Hardware Design of VLD Module in AVS Video Decoder

作　　者：郑军[1] 

机构地区：[1]同济大学通信软件及专用集成电路设计中心,上海200092

出　　处：《现代电子技术》2008年第24期24-26,共3页Modern Electronics Technique

摘　　要：AVS是我国自主制定的音视频编码技术标准。提出一种新的适用于AVS视频解码的变字长解码(VLD)结构,重点研究AVS变字长码的特点,通过合理的码字分割解决码字的存储问题,采用桶式移位器,使得每个时钟能处理1个码字。采用Verilog语言进行设计、模拟,并通过了FPGA验证。采用0.18μm CMOS工艺库综合,在50 MHz的时钟频率下工作时电路规模达到1.6万门左右。AVS is the audio and video standard of China. A novel architecture for Variable Length Decoding （VLD） algorithm for AVS video decoder is proposed in the paper. According to the characteristics of AVS DCT coefficients table, the storage of code word is solved by proper code word partitioning. Barrel shift register is used so that each code word can be processed in one clock period. The module is designed, simulated based on Verilog HDL. The whole design has been verified by FPGA. The VLD is synthesized with 0. 25μm CMOS cell library, and is implemented in 16,000 gates when operating at 50MHz.

关 键 词：AVS视频标准 变长解码 FPGA VERILOG HDL 

分 类 号：TP368.1[自动化与计算机技术—计算机系统结构]