基于随机掩码的AES算法抗DPA攻击硬件实现  

DPA Resistant Hardware Implementation of AES Based on Masking

作　　者：刘海清[1] 陆洪毅[1] 童元满[1] 

机构地区：[1]国防科技大学计算机学院

出　　处：《信息网络安全》2008年第11期51-54,共4页Netinfo Security

基　　金：国家自然科学基金"抗功耗攻击芯片关键技术研究"(60706026)

摘　　要：该文提出了一种基于随机掩码的抗DPA(Differential Power Analysis)攻击的AES算法硬件实现方案。基于随机掩码的AES算法实现中最为关键之处就是唯一的非线性变换即S盒(SubBytes)的实现,该文将S盒中有限域GF(28)上的求逆转换到GF(24)和GF(22)上进行,有效实现了掩码防护。在该文的实现中,所有的中间结果均被随机掩码,证明了该文中AES算法实现能够抗DPA攻击,基于此掩码方案,给出了AES协处理器体系结构,设计实现128密钥的AES协处理器。在0.18μm工艺下,协处理器面积为0.298mm2;在100MHz频率下,加解密吞吐率达到了1.16Gbps。DPA （Differential Power Analysis） attack resistant hardware implementation of AES algorithm based on random masking is proposed. The key of masked implementation of AES is to mask the only non-linear transformation, SubBytes. The inversion over GF（28） is transformed to the computations over GF（24） and GF（22） In GF（22）, the inversion is linear to masking. So all the transformations in AES are masked efficiently. In the proposed approach, all the intermediate results were masked by random values. Theoretic analysis showed that this approach was secure against DPA attack. AES coprocessor based on the proposed masking scheme was implemented. Using 0.18 μ m CMOS technology, area of the coprocessor is 0.298mm2, the maximum frequency is 100MHz, throughput of the data encryption is 1.16Gbps.

关 键 词：DPA AES 随机掩码 有限域 

分 类 号：TP393.08[自动化与计算机技术—计算机应用技术]