Implementation of low-swing differential interface circuits for high-speed on-chip asynchronous interconnection  

作　　者：QIAO Fei YANG HuaZhong HUANG Gang WANG Hui 

机构地区：[1]NICS Group, Department of Electronic Engineering, Tsinghua University, Beijing 100084, China

出　　处：《Science in China(Series F)》2008年第7期975-984,共10页中国科学（F辑英文版）

基　　金：the 973 Program of China (Grant No.G1999032903);the National Science Fund for Distinguished Young Scholars (Grant No.60025101);the Major Program of National Natural Science Foundation of China (Grant No.90707002)

摘　　要：A novel low-swing interface circuit for high-speed on-chip asynchronous interconnection is proposed in this paper. It takes a differential level-triggered latch to recover digital signal with ultra low-swing voltage less than 50 mV, and the driver part of the interface circuit is optimized for low power using the driver-array method, With a capacity to work up to 500 MHz, the proposed circuit, which is simulated and fabricated using SMIC 0.18-pm 1.8-V digital CMOS technology, consumes less power than previously reported designs.A novel low-swing interface circuit for high-speed on-chip asynchronous interconnection is proposed in this paper. It takes a differential level-triggered latch to recover digital signal with ultra low-swing voltage less than 50 mV, and the driver part of the interface circuit is optimized for low power using the driver-array method, With a capacity to work up to 500 MHz, the proposed circuit, which is simulated and fabricated using SMIC 0.18-pm 1.8-V digital CMOS technology, consumes less power than previously reported designs.

关 键 词：low power circuit low-swing interface differential signaling tapered-buffer INTERCONNECT asynchronous circuit 

分 类 号：TN70[电子电信—电路与系统]