AVS帧内预测算法分析及VLSI实现  

Algorithm Analysis and VLSI Implementation of Intra Prediction for AVS High-Definition Video Decoder

作　　者：李霞[1] 黄玄[1] 周莉[1] 陈杰[1] 

机构地区：[1]中国科学院微电子研究所,北京100029

出　　处：《微电子学与计算机》2009年第1期29-33,共5页Microelectronics & Computer

基　　金：国家自然科学基金项目(60425413)

摘　　要：文中提出了一种应用于AVS高清实时解码器的VLSI实现.分析了AVS帧内预测算法的特点,提出了一种所有亮度预测模式和前三种色度预测模式通用的运算单元,为第四种色度预测模式设计了独立的运算单元,并充分复用样本寄存器的方法,提高了资源利用率.该VLSI实现每个时钟周期输出8个预测数据,采用0.18μmCMOS工艺库综合,电路规模为4.4万门,最高工作频率200MHz.An VLSI implementation of intra prediction for AVS High-Definition video decoder is present in this paper. The features of the algorithm of intra prediction are analyzed completely and a general calculate unit is proposed which is used by all the prediction modes except plane mode. The methods of fully reusing registers are adopted to minimize area. The implementation is described in Verilog HDL, simulated with ModelSim and synthesized using 0.18um CMOS cells library by Synopsys Design Compiler. The circuit totally costs about 44k logic gates when working frequency is set to 200MHz. The circuit can output 8 prediction data per cycle.

关 键 词：AVS 帧内预测 高清 解码 VLSI 

分 类 号：TN4[电子电信—微电子学与固体电子学]