雷达视频信号模拟器的硬件设计与实现  

Hardware design and implementation of a radar video signal simulator

作　　者：任勇峰[1] 李圣昆[1] 刘鑫[1] 刘东海[1] 

机构地区：[1]中北大学电子测试技术国家重点实验室,山西太原030051

出　　处：《电子技术应用》2009年第1期67-69,74,共4页Application of Electronic Technique

摘　　要：一种基于TMS320C6713和FPGA的雷达视频信号模拟器,给出了一种可实时模拟多批次目标回波的雷达信号模拟器的实现方案。重点介绍了系统的硬件电路及其实现,并提出一种自适应单环总线结构,用于数据的快速下载。其视频信号的生成过程不是像大多视频模拟器的杂波数据那样通过USB或PCI总线将PC机的数据实时地传输至硬件电路的缓存单元,而是通过上述总线将杂波、噪声及目标参数等数据预先一次性下载至硬件电路的Flash存储器中,生成视频信号时,各通道分别从对应的Flash中读取数据,这样,系统的最大数据吞吐量就可达到240MB/s,完全满足视频信号产生的实时性要求。This paper introduces a kind of video signal simulator based on DSP （TMS320C6713） and FPGA. Highlighting hardware circuit and its realization of the system, a self-adaptive single-ring bus is proposed to download clutter and noise data quickly. In the process of generating the video signal, clutter, noise and objectives parameters are downloaded into flash memories one-timely instead of downloading clutter data real-timely into via USB or PCI bus to cache module on hardware circuit as used in most simulator. Data for each channel are read from corresponding Flash to produce video signal real-timely. In this mode, the maximum data handling capability of the system can reach 240 MB/s, which can fully meet the real-time video signal simulation.

关 键 词：视频信号 数字信号处理 总线 FLASH 

分 类 号：TN409[电子电信—微电子学与固体电子学]