基于FPGA的RS编码器的设计与实现  

The Implementation and Design of RS Encoder Based on FPGA

作　　者：何秋阳[1] 

机构地区：[1]南京邮电大学通信与信息工程学院,江苏南京210003

出　　处：《电子科技》2009年第2期44-46,50,共4页Electronic Science and Technology

摘　　要：RS码是线性分组码中一种典型的纠错码,既能纠正随机错误,也能纠正突发错误,在现代通信领域越来越受到重视。文中介绍基于FPGA使用Verilog-HDL语言的RS(15,9)编码器的设计方法,并在QuartusⅡ5.0软件环境下进行了功能仿真,仿真结果与理论分析相一致,该设计方法对实现任意长度的RS编码有重要参考价值。RS code is an important linear block code widely used in modern digital communications. It can correct both random and bursty errors. The design in this paper is based on an FPGA, using Verilog-HDL right RS（ 15, 9） coding language description and is simulated in the QuartusⅡ 5.0 software environment. Simulation results agree with theoretical analysis. This design is of great significance to the realization of RS coding of arbitrary length.

关 键 词：RS编码 FPGA VERILOG HDL 

分 类 号：TN762[电子电信—电路与系统]