基于FPGA的线阵CCD驱动时序及模拟信号处理的设计  

Design of the time driving and analog signal processing for linear CCD based on FPGA

作　　者：张殿富[1] 赵源[2] 

机构地区：[1]武警工程学院通信与信息技术研究所,西安710086 [2]武警工程学院研究生大队,西安710086

出　　处：《电子设计工程》2009年第1期41-43,共3页Electronic Design Engineering

摘　　要：为保证线阵CCD在图像测量中正常、稳定工作,必须设计出适合其工作的时序驱动电路。在分析TCD1501D线阵CCD驱动时序关系的基础上,通过分析CCD输出的图像信号[1],给出了内、外相关双采样的时序控制。最后,利用quartus7.2软件平台结合VHDL语言进行开发,对所需驱动脉冲进行仿真设计。仿真结果表明,该驱动电路简单、功耗小、成本低、抗干扰能力强,适用于设备小型化的要求。Circuits of time driving pulse is designed well in order that the linear CCD is working stable in image measuring. In the base of analyzing the driving pulse and time sequence of TCD 1501D linear CCD,by analyzing the output image signal of CCD,the paper gives out CDS circuit in and out of the CCD.At last,the required time sequence driving is simulated accurately by the use of development platform of Quartus II 7.2 combining with VHDL.The result of the simulation indicates that the driving circuit is characterized by simple framework,low power consumption,and strong antivjamming ability ,which meet the demand of miniaturization for the project.

关 键 词：线阵CCD 现场可编程逻辑器件(FPGA) 相关双采样 驱动时序 

分 类 号：TN386[电子电信—物理电子学]