SDH/SONET支路时钟抖动衰减数字锁相环设计  

Design of SDH/SONET Tributary Clock Jitter Attenuation Digital Phase Lock Loop

作　　者：叶波 罗敏 王紫石[3] 

机构地区：[1]上海士博微电子股份有限公司,上海201204 [2]朗讯科技光网络有限公司,上海200233 [3]复旦大学信息学院,上海200433

出　　处：《半导体技术》2009年第1期27-30,共4页Semiconductor Technology

摘　　要：提出了一种新的光纤通信网络中SDH/SONET支路时钟抖动衰减设计方法。采用全数字锁相环技术和可编程的方法,根据不同类型的PDH信号,配置相应的增益和衰减因子,使得时钟的抖动衰减收敛速度可调节,能快速的达到国际电信联盟ITU-T标准规定的抖动范围。对于E3信号,滤波组合为100 Hz^800 kHz时,最大峰峰抖动为0.05 UI,滤波组合为10~800 kHz时,最大峰峰抖动小于10-3UI。该方法电路实现结构简单,可广泛应用于光纤通信领域。A novel design of SDH/SONET tributary clock jitter attenuation in optical network communications was presented. Digital phase lock loop technology and programming method were used. Gain and damping factor were programmed according to different types of PDH signals so that digital jitter attenuation convergence could be adjusted, and it could quickly go to the jitter scope defined in ITU-T standard. For E3 signal, Maximum peak-peak jitter is 0.05 UI when the filter characteristics combination is 100 Hz - 800 kHz and maximum peak-peak jitter is less than 10^-3 UI when the filter characteristics combination is 10 - 800 kHz. The circuit realization is very simplified and it can be widely used in optical network communications.

关 键 词：数字抖动 衰减 数字锁相环 

分 类 号：TN492[电子电信—微电子学与固体电子学] TN913.8