深亚微米ASIC设计中的静态时序分析  

Static Timing Analysis Used in Deep Submicron ASIC Design

作　　者：廖军和[1] 叶兵[1] 

机构地区：[1]合肥工业大学微电子学,合肥230009

出　　处：《半导体技术》2009年第1期45-48,共4页Semiconductor Technology

摘　　要：随着集成电路的飞速发展,芯片能否进行全面成功的静态时序分析已成为其保证是否能正常工作的关键。描述了静态时序分析的原理,并以准同步数字系列(PDH)传输系统中16路E1 EoPDH(ethernet over PDH)转换器芯片为例,详细介绍了针对时钟定义、端口约束等关键问题的时序约束策略。结果表明,静态时序分析对该芯片的时序收敛进行了很好的验证。With the fast development of the IC, whether chips can be conducted into a comprehensive success of static timing analysis becomes the key for ensuring normal work. The principle of static timing analysis （STA） was presented, and a detailed description of STA application in the design of 16 E1 EoPDH used in PDH system was given. These strategies are used to resolve clock definition, port constraints and other critical problems. Result shows that timing requirements are well met by STA.

关 键 词：ASIC设计 时序约束 时序路径 静态时序分析 

分 类 号：TN402[电子电信—微电子学与固体电子学]