用于流水线A/D转换器的改进型数字自校准算法  

Improved Digital Calibration Arithmetic for Pipelined A/D Converter

作　　者：钱黎明[1] 姚建楠[1] 吴金[1] 李冰[1] 

机构地区：[1]东南大学集成电路学院,南京210096

出　　处：《微电子学》2009年第1期111-115,共5页Microelectronics

摘　　要：数字自校准算法在高精度流水线ADC中应用越来越广泛。目前,基于数字自校准算法的流水线ADC的结构一般都是1.5位/级。基于对各种结构优缺点的分析,选择在芯片功耗和面积方面有很强优势的2位/级结构,并设计了一种符合这种结构的改进型数字自校准算法。这种改进算法解决了目前数字自校准算法中校准参数不准确的问题,使校准输出后的数据准确度更高。实验结果表明,该改进型数字自校准算法使系统的线性度有了很大的提升。Digital calibration arithmetic has found wide applications in high precision pipelined A/D converter. The structure of pipelined ADC using digital calibration is usually 1.5-bit/stage. Based on the analysis of advantages and disadvantages of different structures, a 2-bit/stage was adopted, which had superiority in power consumption and chip size, and an improved digital calibration arithmetic was designed for this structure, which solved the prob- lem of inaccuracy of calibration coefficients in exsiting digital calibration arithmetics, making the calibrated output data more accurate. Experimental results indicated that the proposed digital calibration arithmetic could significantly improve the linearity of the system.

关 键 词：流水线A/D转换器 数字自校准算法 2位/级结构 线性度 

分 类 号：TN453[电子电信—微电子学与固体电子学]