基于BIST的动态可重构FPGA的时延故障测试方法  

BIST-Based Delay-Fault Testing in Dynamic Reconfiguration FPGAs

作　　者：何怡刚[1] 杜社会[1] 阳辉[1] 方葛丰[1] 

机构地区：[1]湖南大学电气与信息工程学院,湖南长沙410082

出　　处：《计算机测量与控制》2009年第1期5-8,共4页Computer Measurement &Control

基　　金：国家自然科学基金资助项目(50677014);高校博士点基金资助项目(20060532002);国家863计划基金资助项目(2006AA04A104);湖南省科技计划基金资助项目(06JJ2024);教育部新世纪优秀人才支持计划(NCET-04-0767)资助

摘　　要：FPGA市场已经进入极速发展时代,不同的销售商已向市场投入更多更快的FPGA器件。随着FPGA器件的迅速发展,FP-GA的密度和复杂程度也越来越高,使大量的故障难以使用传统方法进行测试,因此,对FPGA器件的故障测试和故障诊断方法进行更全面的研究具有重要意义。为此重点研究了动态重构FPGA及其基本结构、特点;在此基础上探讨了基于BIST技术的FPGA时延故障测试方法,并成功应用于Lattice ORCA 2C系列FPGA中。实验证明,该BIST方法是可行且有效的,并且不需要昂贵的ATE设备。The FPGA market has evolved at an extremely rapid pace with larger and faster devices being released to the industry by different vendors. With the fast expand of FPGA devices, the structure of FPGA becomes more complex, a large number of faults is difficult to use traditional methods for testing, Therefore, the FPGA device fault testing and fault diagnosis method for a more comprehensive study is of great significance. This paper presents a basic structure and feature of currently available dynamically reconfigurable FPGA devices. We present the BIST--Based delay--fault testing approach for FPGAs. We have successfully implemented this BIST approach on the ORCA 2C series FPGA. Our approach is based on B/ST, is comprehensive, and does not require expensive ATE.

关 键 词：BIST FPGA 动态可重构 时延故障 

分 类 号：TP407[自动化与计算机技术]