可切换式TAM结构的快速SoC测试方法  

High-speed SoC test with switching TAM

作　　者：谢元斌[1] 高海霞[1] 潘伟涛[1] 

机构地区：[1]西安电子科技大学微电子学院,陕西西安710071

出　　处：《西安电子科技大学学报》2009年第1期38-42,共5页Journal of Xidian University

基　　金：陕西省自然科学基础研究计划资助(2005F30);西安应用材料创新基金资助(XA-AM-200814)

摘　　要：由于现有TAM(Test Access Mechanism)结构中,被测IP(Intellectual Property)核都是固定地连接在某些TAM总线上,经常会导致测试资源浪费,故提出了可切换式TAM结构.某些IP核通过切换电路挂接在多组TAM上,可以使用多组TAM来完成对一个IP核的测试,减少了空闲时间,缩短了测试用时.按特定的排序规则,采用0-1规划先给每个IP核分配一组TAM,再采用一种启发性搜索算法,挑选合适的IP核使用多组TAM测试.对ITC2002基准电路的实验结果表明,该方法的测试用时较小.There are several TAM architectures with each IP core connected with only one TAM. In this paper, the switching TAM architecture is presented in which each IP core can be connected with one TAM directly or more TAMs with a switching circuit. So some IP cores can be tested by several TAMs, which will reduce the idle time and test time effectively. By 0-1 programming, which is restricted in some given conditions, each IP core is allocated to a TAM, and then a heuristic search arithmetic is used to pick out some appropriate IP cores which could be tested by several TAMs. The test time of our approach on ITC2002 benchmark circuits is less than that of some other approaches.

关 键 词：测试访问机制 测试调度 测试用时 0-1规划 

分 类 号：TP206[自动化与计算机技术—检测技术与自动化装置]