基于JTAG的电路板可测性设计分析技术  

Optimal Testability Design of Circuit Boards Based on JTAG

作　　者：刘冲[1] 汪健甄[1] 张琳[1] 

机构地区：[1]中航工业洛阳电光设备研究所,河南洛阳471009

出　　处：《电光与控制》2009年第3期79-82,共4页Electronics Optics & Control

摘　　要：电路板的可测性和设计复杂性是一对矛盾,由此提出了基于网络表文件的可测性设计优化算法,可在改善电路板测试性的同时,最大限度地降低电路板的设计复杂性。该算法用Matlab来实现,通过对电路板网络表文件的数学分析,确定用最少的边界扫描器件实现对电路网络的一个最大覆盖,从而改善电路板的测试性,大幅度提高电路板的测试覆盖率。最后,利用算法对某电路板进行了可测性分析,试验表明对器件进行了有效的定位,从而为设计工程师进行可测性设计提供了参考和方向。The Design For Testability （DFT） and design complexity of a circuit board are two sides of a coin,thus we put forward an optimal algorithm of DFT based on the circuit board＇ s datasheet document, which can not only improve the board＇ s testability, but also reduce the design complexity as far as possible. The algorithm was realized by using Matlab. Through analyzing the circuit board＇ s datasheet document, we determined to use the least quantity of Boundary Scan （BS） devices to make the largest coverage to the circuit network. Therefore, the fault detection rate was improved to a great extent. The algorithm was used in analyzing the testability of a certain circuit board. The test result showed that this optimal algorithm was effective for component location, and thus may supply a reference for design engineers in testability design.

关 键 词：电路板 可测性设计 网络表 边界扫描 

分 类 号：V271.4[航空宇航科学与技术—飞行器设计] TN407[电子电信—微电子学与固体电子学]