基于Verilog HDL的SPWM全数字算法的FPGA实现  

FPGA realization of SPWM entire digital algorithm based on Verilog HDL

作　　者：丁电宽[1] 梁建均[1] 王文奇[1] 杨荣杰[1] 

机构地区：[1]安阳师范学院电气电子信息工程系,河南安阳455002

出　　处：《电子技术应用》2009年第3期58-61,65,共5页Application of Electronic Technique

摘　　要：在详细阐述正弦脉宽调制算法的基础上,结合DDS技术,以Actel FPGA作为控制核心,通过自然采样法比较1个三角载波和3个相位差为1200的正弦波,利用Verilog HDL语言实现死区时间可调的SPWM全数字算法,并在Fushion StartKit开发板上实现SPWM全数字算法。通过逻辑分析仪和数字存储示波器得到了验证,为该技术进一步应用和推广提供了一个良好的开放平台。On the basis of explaining the SPWM algorithm, this paper combines with DDS technology, puts Actel FPGA as the controlling core,compares a triangular earrier with 3 sine wave with 120° phase, and achieves entire digital algorithm SPWM on development board of Fushion StartKit.broad. Through the logic analyzer and digital storage oscilloscope,thls technology has been verified. This paper provides a good platform for, the application of technology to further promote.

关 键 词：Actel FPGA SPWM DDS VERILOG HDL 

分 类 号：TP273[自动化与计算机技术—检测技术与自动化装置]