10Gbit/s CMOS高增益限幅放大器设计  

Design of a 10 Gbit/s CMOS High Gain Limiting Amplifier

作　　者：陈准[1] 冯军[1] 

机构地区：[1]东南大学射频与光电集成电路研究所,南京210096

出　　处：《电子器件》2009年第1期65-67,共3页Chinese Journal of Electron Devices

摘　　要：利用UMC 0.13μm CMOS工艺设计了10 Gbit/s CMOS高增益限幅放大器。本次设计采用五级改进的Cherry-Hooper结构来提高电路的带宽增益积,运用两级输出缓冲来减少信号的上升下降时间。后仿真结果表明,在1.2 V的供电电压下,电路的功耗为70.8 mW,获得了58.7 dB的增益和9 GHz的-3 dB带宽。输入动态范围为46 dB(6 mVpp^1 200mVpp)时,输出幅度保持在600 mVpp,上升下降时间(10%~90%)为29 ps。芯片的核心面积仅为285.8μm×148.9μm,总面积为665.3μm×515.3μm。A 10 Gbit/s CMOS high gain limiting amplifier is designed in UMC 0.13 μm CMOS technology.In proposed design five stages of modified Cherry-Hooper configuration is employed to increase the gain-bandwidth product and two stages of output buffer to decrease the rise and fall time.The post simulation shows the power dissipation is 70.8 mW with the supply voltage of 1.2 V.The limiting amplifier has achieved a gain of 58.7 dB and a-3 dB bandwidth of 9 GHz.An input dynamic rang is 46 dB（6 mVpp～1 200 mVpp） with constant output swing 600 mVpp.The rise and fall time（10%～90%） is 29 ps.The core area is only 285.8 μm×148.9 μm and the chip die area is 665.3 μm×515.3 μm.

关 键 词：光纤通信 限幅放大器 Cherry-Hooper结构 上升下降时间 0.13μmCMOS工艺 

分 类 号：TN929.11[电子电信—通信与信息系统]