一种高性能1024点fft算法的电路设计  

An Effective Hardware Architecture of 1024 point FFT

作　　者：张锦红[1] 叶甜春[1] 徐建华[1] 

机构地区：[1]中国科学院微电子研究所,北京100029

出　　处：《微计算机信息》2009年第8期303-304,234,共3页Control & Automation

摘　　要：本文针对高速大规模FFT处理器的需求提出了一种基-4按时间抽取的双通道FFT算法的硬件结构,采用4块小容量双端口SRAM代替一块大容量SRAM的设计思路以及多级流水结构。此结构能同时从四个存储器中并行存取蝶形运算的4个操作数和4个中间结果,极大的提高了处理速度。用CORDIC算法代替传统的乘法器,节省了大量的存放旋转因子的ROM表格和乘法器等硬件资源从而节省了电路面积,并设置了通道关断技术,进一步节省了功耗。经硬件验证,在系统时钟为100MHz时,1024点20位复数FFT计算时间平均为10us左右。In modern signal process system, FFT processor is the very important part.This article gives out a hardware FFT algorithm which bases on 4 point DIT FFT.Here 4 small SRAM are used to replace the large one. The pipeline technique is used to make the FFT algorithm much faster than traditional method. CORDIC is also used to replace multiplex to save ROM and hardware cost. ＂Channel off＂ technique is also used to save power. The system has been verified on FPGA and it only uses 10us to finish 1024 point FFT with 100M clock in average.

关 键 词：基-4FFT CORDIC 双端口SRAM 双通道 

分 类 号：TN47[电子电信—微电子学与固体电子学]