基于事件结构的SystemVerilog指称语义  

Denotational Semantics of SystemVerilog based on Extended Bundle Event Structure

作　　者：贺彦琨[1] 

机构地区：[1]兰州大学,信息科学与工程学院

出　　处：《微计算机信息》2009年第9期171-172,165,共3页Control & Automation

摘　　要：本文利用形式化的方法对System Verilog的指称语义进行研究,采用EBES(extended bundle event structure)作为抽象模型,以便更好的描述System Verilog真并发的特点。我们的主要工作是:首先,通过对System Verilog语言的认真学习,从中抽取出一个尽可能多的包含其语法的真并发子集;其次,利用进程代数LOTOS描述其基于EBES模型的指称语义,以提供一个准确的、无二义性的System Verilog文档,避免硬件设计中的逻辑性错误。In this paper, denotational semantics of SystemVerilog is studied in formal ways, and EBES （extended bundle event structure） is adopted as the model to describe the true concurrency of System Verilog better. The paper provides a true concurrency subset from System Verilog, and then presents denotational semantics of the subset based on the EBES, which is described in the process algebra format. Our aim is offering a precise, unambiguous semantics for SystemVerilog in order to avoid logic mistakes in hardware designs.

关 键 词：SYSTEMVERILOG 指称语义 EBES 进程代数 

分 类 号：TP302[自动化与计算机技术—计算机系统结构]