双阈值VLSI低测试功耗方法研究  

Research on novel low test power based on two threshold VLSI

作　　者：邢军[1] 王冠军 

机构地区：[1]牡丹江师范学院计算机科学与技术系,黑龙江牡丹江157012 [2]哈尔滨工程大学计算机科学与技术学院,哈尔滨150001

出　　处：《计算机应用研究》2009年第4期1402-1404,1408,共4页Application Research of Computers

基　　金：国家自然科学基金资助项目(69973014)

摘　　要：提出一种测试功耗优化的新方法,它通过阈值门电路调节和漏电流优化两种方法相结合来降低静态功耗。通过算法寻找电路的关键路径,去除伪路径,然后在关键电路上设置低阈值门电路,在非关键电路上设置高阈值门电路(不违反时序约束的前提下),利用测试向量的无关位特性来调整测试向量和测试架构,达到降低漏电流的目的。通过以上两种途径,整体上达到功耗优化的结果,实验结果证实了本方法的有效性。This paper proposed a new test power consumption optimization approach, it reduced the static power consuming through voltage sealing and leakage optimization. To find the critical path through the algorithm, eliminate the false path, and then set low threshold voltage on the critical path, set high threshold voltage on the non-critical paths（ without violating the timing constraints）. To regular the test vector and modify the test architecture based on the don＇ t care bits, so it could reduce the leakage current. With the two.ways, got a better optimization result. The experiment shows the efficiency.

关 键 词：测试功耗 电压调节 漏电流优化 测试向量 

分 类 号：TP391.4[自动化与计算机技术—计算机应用技术]