基于DSP Builder的并行中值滤波算法的设计与实现  

Implementation of parallel median filtering algorithm based on DSP Builder

作　　者：罗坤[1] 肖铁军[1] 

机构地区：[1]江苏大学计算机学院,江苏镇江212013

出　　处：《计算机工程与设计》2009年第6期1413-1416,共4页Computer Engineering and Design

摘　　要：研究了一种适合采用现场可编程逻辑(FPGA)消除图像随机噪声的算法以及用DSPBuilder实现该算法的硬件电路设计。结合FPGA并行计算的特点,采用滑动窗口和模块化设计思想,对常规中值滤波算法的结构进行改进,提高了算法的运算速度,简化硬件结构。通过仿真和FPGA验证结果表明,该算法可以有效消除图像随机噪声,同时处理延时短,可以满足嵌入式系统的实时性要求。Elimination random noise of image based on FPGA and how to design its hardware with DSP builder are introduced. To obtain high speed and simplify the algorithm, many techniques are used, such as sliding window, modular design method, parallel calculation. The results of simulation and FPGA verification show that this design performs very efficiently on random noise of image elimination. In addition, the algorithm will meet the real-time requirement of embedded systems.

关 键 词：DSP BUILDER 滑动窗口 FPGA 模块化设计 并行计算 

分 类 号：TP912.3[自动化与计算机技术]