MUX-buffer开关互连结构的FPGA芯片I/O互连设计  

The Design of the FPGA I/O Interconnect with the MUX-buffer Routing Architecture

作　　者：张火文[1] 黄均鼐[2] 李楠[1] 郑国祥[1] 曾韡[1] 

机构地区：[1]复旦大学材料科学系,上海200433 [2]复旦大学专用集成电路与系统国家重点实验室,上海201203

出　　处：《固体电子学研究与进展》2009年第1期93-98,共6页Research & Progress of SSE

摘　　要：硬件结构及电子设计的质量是决定FPGA性能的两个重要因素。针对这两个方面,提出了一种通用的FP-GA芯片I/O互连结构,利用"回线"的终端互补原理对各种互连线的悬空终端进行连接。根据所提出的I/O互连结构的特点,在较少编程点的前提下,减少传输管级联个数,对多路选择器和缓冲器进行优化,提出了一种节省芯片面积且速度较快的基于MUX-Buffer结构的布线开关。该结构已在FPGA芯片中实现,对I/O互连的仿真及测试结果表明,所提出的结构及电路实现具有很好的延时可预测性,与常规MUX结构相比,面积-延时乘积降低了10%左右。The quality of the architecture and the electrical design are two important factors to determine the performance of an FPGA. Considering this two factors, we propose a novel general architecture of the FPGA input/output interconnect. We utilize the ＂return wire＂ to complete the interconnection of the terminals of the routing wires with the method of ＂terminal Complementary＂. According to the I/O interconnect architecture, we optimize the Multiplexer and Buffer with less programmable interconnection point and less cascaded transistors, and then present a routing switch with less area and high speed based on the MUX-Buffer structure. The design has already implemented in the FPGA chip. The result of the simulation and the testing shows the delay is predictable. Compared to the traditional MUX architecture, it reduces areadelay product by 10%.

关 键 词：现场可编程门阵列 输入/输出互连 回线 布线开关 延时可预测性 

分 类 号：TN47[电子电信—微电子学与固体电子学]