工艺波动致RLC互连延时极值分析  

Extreme value analysis of RLC interconnect delay induced by process variations

作　　者：李建伟[1] 董刚[1] 杨银堂[1] 王增[1] 

机构地区：[1]西安电子科技大学宽禁带半导体材料与器件教育部重点实验室,陕西西安710071

出　　处：《西安电子科技大学学报》2009年第2期301-307,共7页Journal of Xidian University

基　　金：国家自然科学基金资助(60606006);国家杰出青年基金资助(60725415);重点实验室基金资助(9140C030102060C0303)

摘　　要：基于等效Elmore延时模型和RLC互连的工艺角分析,提出了工艺波动致RLC互连延时快速极值分析方法,可以用于由工艺波动引起的RLC互连延时变化的最好情况和最坏情况分析.采用该方法针对68 nm,45 nm,36 nm和25 nm工艺节点进行了仿真验证.结果显示,这种新方法误差小速度快,与HSPICE相比误差小于7%,可以应用在快速静态时序分析中.Based on the process corners analysis and equivalent Elmore delay model,a fast extreme value estimation of RLC interconnect delay induced by process variations is presented.It can be used to compute the best-case and worst-case RLC interconnect delay caused by process variations.Simulations for 68 nm,45 nm,36 nm and 25 nm technologies are given.Results show that the new method has the characteristics of a fast calculating speed and high accuracy,and that the proposed method is less than 7% in error compared with the HSPICE.It can be used to analyze the delay limit of the critical path in STA.

关 键 词：工艺波动 RLC互连延时 工艺角 

分 类 号：TN405.97[电子电信—微电子学与固体电子学]