非正则LDPC码部分并行译码器设计  

Partially-Parallel Decoder of Irregular Low Density Parity Check Codes

作　　者：张彬[1] 胡剑浩[1] 刘文焘[1] 李少谦[1] 

机构地区：[1]电子科技大学通信抗干扰技术国家级重点实验室,成都610054

出　　处：《电子科技大学学报》2007年第S2期1121-1124,共4页Journal of University of Electronic Science and Technology of China

摘　　要：由于卓越的纠错性能,LDPC码得到了越来越多的关注,以有效的硬件实现LDPC译码器也成为了一个重要的课题。该文根据BP_Based译码算法,提出了一种部分并行的非正则LDPC译码器结构。它通过列交换处理,校验矩阵形成了k个子矩阵,子矩阵之间数据以并行机制处理。这种实现方法解决了当校验矩阵为完全随机时,硬件资源和数据吞吐量平衡的问题。该译码器码长为3 944 b,使用Xilinx的Virtex-ⅡPro70芯片实现。结果表明,当迭代次数为20次时,数据吞吐量达到了6.5 Mb/s。Due to the excellent performance,Low-Density Parity-Check(LDPC)codes have received more and more attentions.The hardware implementation of LDPC decoder becomes a crucial issue recently.According to the BP_Based algorithm,a partially-parallel LDPC decoder architecture is proposed in this paper.By column exchanging,the parity check matrix is divided into k sub-matrice.Data is processed parallelly between the sub-matrice.The trade-off between hardware resource and data throughout can be achieved with this architecture for random parity check matrix.The decoder,with 3 944 b in data length has been implemented with the device FPGA Virtex-ⅡPro70.The results show that the maximum throughout of this decoder is 6.5 Mb/s with 20 iterations.

关 键 词：BP_Based译码算法 LDPC译码器 校验矩阵 部分并行结构 

分 类 号：TN764[电子电信—电路与系统]