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作 者:董文娟[1] 王宏义[1] 韩建涛[1] 陈曾平[1]
机构地区:[1]国防科技大学ATR重点实验室,长沙410073
出 处:《计算机工程》2009年第7期20-22,共3页Computer Engineering
基 金:国家"863"计划基金资助项目(2007AA703406;2007AA703121)
摘 要:针对大视场高分辨率光电实时处理系统实时性问题,分析光电弱小目标检测的任务特点,从处理器节点、存储器和连接处理器节点的网络3个方面分析实时并行处理机的设计要点,设计一种基于SRIO技术的双DSP+FPGA并行处理机。FPGA实现低层处理算法,DSP实现高层处理算法,任务划分采用区域分解并行算法,实验结果证明该设计具有可行性。In order to solve real-time performance of large field, high resolution optoelectronic processing system, this paper analyzes the characteristic of task of detecting optoelectronic small weak targets and the primary principle of design of real-time parallel processor through three factors such as processor nodes, memory and the network connecting the processor nodes. It puts forward a parallel processor consists of double DSP + FPGA based on SRIO technology. The low level algorithm is realized with FPGA and the high level algorithm is realized by DSPs. A region-decomposing parallel algorithm which is fit for digital image processing is adopted for dividing image-processing task, Experimental result shows the feasibility of the design.
分 类 号:TN911.73[电子电信—通信与信息系统]
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