A 10 Gb/s receiver with half rate period calibration CDR and CTLE/DFE combiner  

作　　者：高茁 杨宗仁 赵莹 杨袆 张璐 黄令仪 胡伟武 

机构地区：[1]Institute of Computing Technology, Chinese Academy of Sciences [2]Graduate University of the Chinese Academy of Sciences

出　　处：《Journal of Semiconductors》2009年第4期106-112,共7页半导体学报（英文版）

基　　金：supported by the State Key Development Program for Basic Research of China (No. 2005CB321600);the National High Technol-ogy Development Research and Program of China (No. 2008AA110901);the National Natural Science Foundation of China (Nos.60801045, 60803029, 60673146, 60603049);the Beijing Natural Science Foundation (No. 4072024)

摘　　要：This paper presents the design of a 10 Gb/s low power wire-line receiver in the 65 nm CMOS process with 1 V supply voltage. The receiver occupies 300×500 μm2. With the novel half rate period calibration clock data recovery （CDR） circuit, the receiver consumes 52 mW power. The receiver can compensate a wide range of channel loss by combining the low power wideband programmable continuous time linear equalizer （CTLE） and decision feedback equalizer （DFE）.This paper presents the design of a 10 Gb/s low power wire-line receiver in the 65 nm CMOS process with 1 V supply voltage. The receiver occupies 300×500 μm2. With the novel half rate period calibration clock data recovery （CDR） circuit, the receiver consumes 52 mW power. The receiver can compensate a wide range of channel loss by combining the low power wideband programmable continuous time linear equalizer （CTLE） and decision feedback equalizer （DFE）.

关 键 词：serial link RECEIVER CDR EQUALIZER 

分 类 号：TN851[电子电信—信息与通信工程]