Implementation and noise optimization of a 433 MHz low power CMOS LNA  

433MHz低功耗CMOS LNA的噪声优化与实现(英文)

作　　者：吴秀山[1,2] 王志功[1] 李智群[1] 李青[2] 

机构地区：[1]东南大学射频与光电集成电路研究所,南京210096 [2]中国计量学院机电工程学院,杭州310018

出　　处：《Journal of Southeast University(English Edition)》2009年第1期9-12,共4页东南大学学报（英文版）

基　　金：The National Natural Science Foundation of China (No.60772008);the Key Science and Technology Program of Zhejiang Province(No.G2006C13024)

摘　　要：A low power 433 MHz CMOS （complementary metal- oxide-semiconductor transistor） low noise amplifier（LNA）, used for an ISM （ industrial-scientific-medical ） receiver, is implemented in a 0. 18 μm SMIC mixed-signal and RF （ radio frequency） CMOS process. The optimal noise performance of the CMOS LNA is achieved by adjusting the source degeneration inductance and by inserting an appropriate capacitance in parallel with the input transistor of the LNA. The measured results show that at 431 MHz the LNA has a noise figure of 2.4 dB. The S21 is equal to 16 dB, S11 = -11 dB, S22 = -9 dB, and the inverse isolation is 35 dB. The measured input 1-dB compression point （PtdB） and input third-order intermodulation product （IIP3）are - 13 dBm and -3 dBm, respectively. The chip area is 0. 55 mm × 1.2 mm and the DC power consumption is only 4 mW under a 1.8 V voltage supply.采用0.18μm SMIC数模混合与射频(RF)CMOS工艺实现了一个应用于ISM(工业、科学和医疗)频段接收机的433MHz低功耗低噪声放大器(LNA)的设计.电路通过调节源级反馈电感和在LNA输入晶体管上并联电容的方法实现了最优的噪声性能.测试结果表明,LNA在431MHz处的噪声系数为2.4dB,S21=16dB,S11=-11dB,S22=-9dB,反向隔离度大于35dB.测量的1-dB压缩点(P1dB)和输入三阶交调(IIP3)分别为-13dBm和-3dBm.芯片面积为0.55mm×1.2mm,在1.8V供电时整个电路功耗仅4mW.

关 键 词：low noise amplifier （LNA） CASCODE low power noise figure noise optimization 

分 类 号：TN929.11[电子电信—通信与信息系统] TP368.1[电子电信—信息与通信工程]