三维片上网络拓扑研究  

Research on Topologic Architecture of Three-Dimensional Network on Chip

作　　者：陈亦欧[1] 胡剑浩[1] 凌翔[1] 

机构地区：[1]电子科技大学通信抗干扰技术国家级重点实验室,成都610054

出　　处：《电信科学》2009年第4期39-44,共6页Telecommunications Science

基　　金：国家"863"计划基金资助项目(No.2007AA01Z291);自然科学基金资助项目(No.60873076)

摘　　要：三维片上网络是集成电路领域的新技术,用于解决目前片上系统集成度越来越高所面临的通信瓶颈。本文介绍了当前三维片上网络的拓扑和相关技术,提出了三种新型的基于DeBruijn图的拓扑,并对各种拓扑的性能参数进行了比较。The three-dimensional network on chip is a new technology in VLSI, in order to solve the communication challenges of system on chip caused by high integration. The state of the art topologies and relative techniques for 3D NoC are introduced in this area, three novel 3D topologies based on De Bruijn graph are proposed, and the performance parameters of these topologies are compared.

关 键 词：片上网络 三维封装 拓扑 

分 类 号：TP393[自动化与计算机技术—计算机应用技术] O157.5[自动化与计算机技术—计算机科学与技术]